Universal chiplet interconnect express (UCIe) is an open industry standard interconnect for a chiplet ecosystem in which chiplets from multiple suppliers can be packaged together. The UCIe 1.0 specification defines interoperability using standard and advanced packaging technologies with planar interconnects. Here we examine the development of UCIe as the bump interconnect pitches reduce with advances in packaging technologies for three-dimensional integration of chiplets. We report a die-to-die solution for the continuum of package bump pitches down to 1 µm, providing circuit architecture details and performance results. Our analysis suggests that—contrary to trends seen in traditional signalling interfaces—the most power-efficient performance for these architectures can be achieved by reducing the frequency as the bump pitch goes down. Our architectural approach provides power, performance and reliability characteristics approaching or exceeding that of a monolithic system-on-chip design as the bump pitch approaches 1 µm.

通用小芯片互连 Express (UCIe) 是一种针对小芯片生态系统的开放式行业标准互连，其中来自多个供应商的小芯片可以封装在一起。UCIe 1.0 规范使用标准和先进封装技术与平面互连来定义互操作性。在这里，我们研究了 UCIe 的发展，因为随着小芯片三维集成封装技术的进步，凸点互连间距不断减小。我们报告了一种芯片到芯片解决方案，可将封装凸块间距连续降至 1 µm，提供电路架构详细信息和性能结果。我们的分析表明，与传统信号接口中看到的趋势相反，这些架构的最节能性能可以通过随着凸块间距减小而降低频率来实现。当凸块间距接近 1 µm 时，我们的架构方法提供的功耗、性能和可靠性特性接近或超过单片片上系统设计。