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Time-space multiplexed photonic-electronic digital multiplier
Photonics Research ( IF 7.6 ) Pub Date : 2024-03-01 , DOI: 10.1364/prj.511389
Wenkai Zhang , Bo Wu , Wentao Gu , Junwei Cheng , hailong zhou , liao chen , Wenchan Dong , Jianji Dong , Xinliang Zhang

Optical computing has shown immense application prospects in the post-Moore era. However, as a crucial component of logic computing, the digital multiplier can only be realized on a small scale in optics, restrained by the limited functionalities and inevitable loss of optical nonlinearity. In this paper, we propose a time-space multiplexed architecture to realize large-scale photonic-electronic digital multiplication. We experimentally demonstrate an 8×2-bit photonic-electronic digital multiplier, and the multiplication with a 32-bit number is further executed at 25 Mbit/s to demonstrate its extensibility and functionality. Moreover, the proposed architecture has the potential for on-chip implementation, and a feasible integration scheme is provided. We believe the time-space multiplexed photonic-electronic digital multiplier will open up a promising avenue for large-scale photonic digital computing.

中文翻译:

时空复用光子电子数字乘法器

光计算在后摩尔时代展现出巨大的应用前景。然而,作为逻辑计算的关键组成部分,数字乘法器由于功能有限和不可避免的光学非线性损失而只能在光学中小规模实现。在本文中,我们提出了一种时空复用架构来实现大规模光子电子数字乘法。我们通过实验演示了8 × 2位光子电子数字乘法器,并进一步以 25 Mbit/s 的速度执行与 32 位数字的乘法,以展示其可扩展性和功能。此外,所提出的架构具有片上实现的潜力,并提供了可行的集成方案。我们相信时空复用光子电子数字乘法器将为大规模光子数字计算开辟一条有前途的途径。
更新日期:2024-03-02
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