We propose a quantum processor architecture, the qubit ‘pipeline’, in which run-time scales additively as functions of circuit depth and run repetitions. Run-time control is applied globally, reducing the complexity of control and interconnect resources. This simplification is achieved by shuttling N-qubit states through a large layered physical array of structures which realise quantum logic gates in stages. Thus, the circuit depth corresponds to the number of layers of structures. Subsequent N-qubit states are ‘pipelined’ densely through the structures to efficiently wield the physical resources for repeated runs. Pipelining thus lends itself to noisy intermediate-scale quantum (NISQ) applications, such as variational quantum eigensolvers, which require numerous repetitions of the same or similar calculations. We illustrate the architecture by describing a realisation in the naturally high-density and scalable silicon spin qubit platform, which includes a universal gate set of sufficient fidelity under realistic assumptions of qubit variability.

我们提出了一种量子处理器架构，即量子位“管道”，其中运行时间作为电路深度和运行重复的函数进行加法缩放。运行时控制在全局范围内应用，降低了控制和互连资源的复杂性。这种简化是通过在大分层物理结构阵列中穿梭N量子位态来实现的，这些结构分阶段实现量子逻辑门。因此，电路深度对应于结构的层数。随后的N量子位状态通过结构密集地“管道化”，以有效地利用物理资源进行重复运行。因此，流水线适用于噪声中等规模量子（NISQ）应用，例如变分量子本征解算器，它需要大量重复相同或相似的计算。我们通过描述自然高密度和可扩展的硅自旋量子位平台的实现来说明该架构，该平台包括在量子位可变性的现实假设下具有足够保真度的通用门集。