A typical machine learning development cycle maximizes performance during model training and then minimizes the memory and area footprint of the trained model for deployment on processing cores, graphics processing units, microcontrollers or custom hardware accelerators. However, this becomes increasingly difficult as machine learning models grow larger and more complex. Here we report a methodology for automatically generating predictor circuits for the classification of tabular data. The approach offers comparable prediction performance to conventional machine learning techniques as substantially fewer hardware resources and power are used. We use an evolutionary algorithm to search over the space of logic gates and automatically generate a classifier circuit with maximized training prediction accuracy, which consists of no more than 300 logic gates. When simulated as a silicon chip, our tiny classifiers use 8–18 times less area and 4–8 times less power than the best-performing machine learning baseline. When implemented as a low-cost chip on a flexible substrate, they occupy 10–75 times less area, consume 13–75 times less power and have 6 times better yield than the most hardware-efficient ML baseline.

典型的机器学习开发周期会在模型训练期间最大限度地提高性能，然后最大限度地减少训练模型的内存和面积占用，以部署在处理核心、图形处理单元、微控制器或定制硬件加速器上。然而，随着机器学习模型变得越来越大、越来越复杂，这变得越来越困难。在这里，我们报告了一种自动生成用于表格数据分类的预测器电路的方法。由于使用的硬件资源和功耗大大减少，该方法提供了与传统机器学习技术相当的预测性能。我们使用进化算法在逻辑门空间中进行搜索，并自动生成训练预测精度最大化的分类器电路，该电路由不超过 300 个逻辑门组成。当模拟为硅芯片时，我们的微型分类器使用的面积比性能最佳的机器学习基准少 8-18 倍，功耗也低 4-8 倍。当在柔性基板上实现为低成本芯片时，与最硬件效率最高的 ML 基准相比，它们占用的面积减少了 10-75 倍，功耗减少了 13-75 倍，产量提高了 6 倍。