We present a general strategy for mapping fermionic systems to quantum hardware with square qubit connectivity which yields low-depth quantum circuits, counted in the number of native two-qubit fSIM gates. We achieve this by leveraging novel operator decomposition and circuit compression techniques paired with specifically chosen low-depth fermion-to-qubit mappings and allow for a high degree of gate cancellations and parallelism. Our mappings retain the flexibility to simultaneously optimize for qubit counts or qubit operator weights and can be used to investigate arbitrary fermionic lattice geometries. We showcase our approach by investigating the tight-binding model, the Fermi-Hubbard model as well as the multi-orbital Hubbard-Kanamori model. We report unprecedentedly low circuit depths per single Trotter layer with up to a $70 \%$ improvement upon previous state-of-the-art. Our compression technique also results in significant reduction of two-qubit gates. We find the lowest gate-counts when applying the XYZ-formalism to the DK mapping. Additionally, we show that our decomposition and compression formalism produces favourable circuits even when no native parameterized two-qubit gates are available.

中文翻译：

---

方格量子硬件上费米子系统的低深度模拟

我们提出了一种将费米子系统映射到具有方形量子位连接的量子硬件的通用策略，该策略产生低深度量子电路，以本机双量子位 fSIM 门的数量计算。我们通过利用新颖的算子分解和电路压缩技术以及专门选择的低深度费米子到量子位映射来实现这一点，并允许高度的门取消和并行性。我们的映射保留了同时优化量子位计数或量子位运算符权重的灵活性，并且可用于研究任意费米子晶格几何形状。我们通过研究紧束缚模型、费米-哈伯德模型以及多轨道哈伯德-金森模型来展示我们的方法。我们报告说，每个 Trotter 层的电路深度前所未有地低，与之前最先进的技术相比，提高了 70%$。我们的压缩技术还可以显着减少两个量子位门。当将 XYZ 形式应用于 DK 映射时，我们发现门数最低。此外，我们表明，即使没有可用的本机参数化两量子位门，我们的分解和压缩形式也会产生有利的电路。