The emergence of technologies such as Artificial Intelligence (AI) and the Internet of Things (IoT) has ushered in the era of big data. The demand for low‐power hardware systems and efficient algorithms has become more imperative. In this study, an ultra‐low‐power dynamic memtransistor based on the charge storage junction Field‐Effect Transistor (FET) with a step‐wise potential barrier is developed. A simple yet efficient device structure allows for analog programming and spontaneous relaxation. The device demonstrated fast speed (tens of nanoseconds (ns)) and low current (in picoamperes (pA)), resulting in ultra‐low programming power (in attojoules (aJ)). Furthermore, the device exhibited high reliability, with a 0.4% cycle‐to‐cycle variation and endurance over 107 pulses, owing to its non‐structural destructive operation process. An operation scheme is developed that enables read on/off and program/inhibition mode for 2T (1 memtransistor‐1 selecting transistor) array. The capability to distinguish temporal data using the device's spontaneous relaxation characteristics is demonstrated. A reservoir computing (RC) system framework is constructed using simulation and verified that the dynamic memtransistor can extract features efficiently from a hand‐written digit dataset. It is anticipated that the developed dynamic memtransistor, with its distinctive temporal characteristics, will play a pivotal role in developing a novel low‐power computing framework.

中文翻译：

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基于电荷存储结 FET 的超低功耗、可靠的动态薄膜晶体管，具有用于节能边缘计算框架的逐步势垒

人工智能（AI）、物联网（IoT）等技术的出现，迎来了大数据时代。对低功耗硬件系统和高效算法的需求变得更加迫切。在这项研究中，开发了一种基于具有阶梯势垒的电荷存储结场效应晶体管（FET）的超低功耗动态薄膜晶体管。简单而高效的设备结构允许模拟编程和自发放松。该器件表现出快速（数十纳秒 (ns)）和低电流（皮安 (pA)），从而实现超低编程功率（阿托焦耳 (aJ)）。此外，该器件表现出高可靠性，周期变化率为 0.4%，耐久性超过 107脉冲，由于其非结构破坏性操作过程。开发了一种操作方案，可实现 2T（1 个记忆晶体管-1 个选择晶体管）阵列的读开/关和编程/禁止模式。演示了使用设备的自发弛豫特性来区分时间数据的能力。通过仿真构建了储层计算（RC）系统框架，并验证了动态存储器可以从手写数字数据集中有效地提取特征。预计所开发的动态存储器以其独特的时间特性，将在开发新型低功耗计算框架中发挥关键作用。