Probabilistic computing is a computing scheme that offers a more efficient approach than conventional complementary metal-oxide–semiconductor (CMOS)-based logic in a variety of applications ranging from optimization to Bayesian inference, and invertible Boolean logic. The probabilistic bit (or p-bit, the base unit of probabilistic computing) is a naturally fluctuating entity that requires tunable stochasticity; by coupling low-barrier stochastic magnetic tunnel junctions (MTJs) with a transistor circuit, a compact implementation is achieved. In this work, by combining stochastic MTJs with 2D-MoS₂ field-effect transistors (FETs), we demonstrate an on-chip realization of a p-bit building block displaying voltage-controllable stochasticity. Supported by circuit simulations, we analyze the three transistor-one magnetic tunnel junction (3T-1MTJ) p-bit design, evaluating how the characteristics of each component influence the overall p-bit output. While the current approach has not reached the level of maturity required to compete with CMOS-compatible MTJ technology, the design rules presented in this work are valuable for future experimental implementations of scaled on-chip p-bit networks with reduced footprint.

概率计算是一种计算方案，在从优化到贝叶斯推理和可逆布尔逻辑等各种应用中，它提供了比传统的基于互补金属氧化物半导体 (CMOS) 的逻辑更有效的方法。概率位（或p位，概率计算的基本单位）是一个自然波动的实体，需要可调的随机性；通过将低势垒随机磁隧道结 (MTJ) 与晶体管电路耦合，实现了紧凑的实现。在这项工作中，通过将随机 MTJ 与 2D-MoS ₂场效应晶体管 (FET) 相结合，我们演示了显示电压可控随机性的 p 位构建块的片上实现。在电路仿真的支持下，我们分析了三晶体管一磁隧道结 (3T-1MTJ) p 位设计，评估每个组件的特性如何影响整体 p 位输出。虽然目前的方法尚未达到与 CMOS 兼容的 MTJ 技术竞争所需的成熟度，但这项工作中提出的设计规则对于未来缩小占地面积的扩展片上 p 位网络的实验实现很有价值。